/*
    Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
    Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>

    Copyright (C) 2009 TurboSight.com

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/firmware.h>

#include "dvb_frontend.h"
#include "ds3000.h"

// qwm add at 2010.4.12
#ifndef __QWM_DGB__
#define __QWM_DGB__
#endif

static int debug;

#define dprintk(args...) \
	do { \
		if (debug) \
			printk(args); \
	} while (0)

/* as of March 2009 current DS3000 firmware version is 1.78 */
/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"

#define DS3000_SAMPLE_RATE 96000 /* in kHz */
#define DS3000_XTAL_FREQ   27000 /* in kHz */

// qwm add at 2010.4.14
static u32	g_auto_tune_cnt    		= 0;
static u32	g_cci_detect;
static s32	g_load_firmware			= 0;
static int ds3000_set_demod(struct dvb_frontend *fe);

/* Register values to initialise the demod in DVB-S mode */
static u8 ds3000_dvbs_init_tab[] = {
	// qwm modified at 2010.4.10
	#if 0
	0x23, 0x05,
	0x08, 0x03,
	0x0c, 0x00,
	0x21, 0x54,
	0x25, 0x82,
	0x27, 0x31,
	0x30, 0x08,
	0x31, 0x40,
	0x32, 0x32,
	0x33, 0x35,
	0x35, 0xff,
	0x3a, 0x00,
	0x37, 0x10,
	0x38, 0x10,
	0x39, 0x02,
	0x42, 0x60,
	0x4a, 0x40,
	0x4b, 0x04,
	0x4d, 0x91,
	0x5d, 0xc8,
	0x50, 0x77,
	0x51, 0x77,
	0x52, 0x36,
	0x53, 0x36,
	0x56, 0x01,
	0x63, 0x43,
	0x64, 0x30,
	0x65, 0x40,
	0x68, 0x26,
	0x69, 0x4c,
	0x70, 0x20,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x40,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x60,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x80,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0xa0,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x1f,
	0x76, 0x00,
	0x77, 0xd1,
	0x78, 0x0c,
	0x79, 0x80,
	0x7f, 0x04,
	0x7c, 0x00,
	0x80, 0x86,
	0x81, 0xa6,
	0x85, 0x04,
	0xcd, 0xf4,
	0x90, 0x33,
	0xa0, 0x44,
	0xc0, 0x18,
	0xc3, 0x10,
	0xc4, 0x08,
	0xc5, 0x80,
	0xc6, 0x80,
	0xc7, 0x0a,
	0xc8, 0x1a,
	0xc9, 0x80,
	0xfe, 0x92,
	0xe0, 0xf8,
	0xe6, 0x8b,
	0xd0, 0x40,
	0xf8, 0x20,
	0xfa, 0x0f,
	0xfd, 0x20,
	0xad, 0x20,
	0xae, 0x07,
	0xb8, 0x00,
	#else
    0x23, 0x05,
    0x08, 0x03,
    0x0c, 0x00,
    0x21, 0x54,
    0x25, 0x82,
    0x27, 0x31,
    0x30, 0x08,
    0x31, 0x40,
    0x32, 0x32,
    0x33, 0x35,
    0x35, 0xff,
    0x3a, 0x00,
    0x37, 0x10,
    0x38, 0x10,
    0x39, 0x02,
    0x42, 0x60,
    0x4a, 0x40,
    0x4b, 0x04,
    0x4d, 0x91,
    0x5d, 0xc8,
    0x50, 0x77,
    0x51, 0x77,
    0x52, 0x36,
    0x53, 0x36,
    0x56, 0x01,
    0x63, 0x47,
    0x64, 0x30,
    0x65, 0x40,
    0x68, 0x26,
    0x69, 0x4c,
    0x70, 0x20,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x40,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x60,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x80,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0xa0,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x1f,
    0x76, 0x00,
    0x77, 0xd1,
    0x78, 0x0c,
    0x79, 0x80,
    0x7f, 0x04,
    0x7c, 0x00,
    0x80, 0x86,
    0x81, 0xa6,
    0x85, 0x04,
    0xcd, 0xf4,
    0x90, 0x33,
    0xa0, 0x44,
    0xc0, 0x18,
    0xc3, 0x10,
    0xc4, 0x08,
    0xc5, 0x80,
    0xc6, 0x80,
    0xc7, 0x0a,
    0xc8, 0x1a,
    0xc9, 0x80,
    0xfe, 0x92,
    0xe0, 0xf8,
    0xe6, 0x8b,
    0xd0, 0x40,
    0xf8, 0x20,
    0xfa, 0x0f,
    0xfd, 0x20,
    0xad, 0x20,
    0xae, 0x07,
    0xb8, 0x00,
	#endif
};

/* Register values to initialise the demod in DVB-S2 mode */
static u8 ds3000_dvbs2_init_tab[] = {
	// qwm modified at 2010.4.10
	#if 0
	0x23, 0x0f,
	0x08, 0x07,
	0x0c, 0x00,
	0x21, 0x54,
	0x25, 0x82,
	0x27, 0x31,
	0x30, 0x08,
	0x31, 0x32,
	0x32, 0x32,
	0x33, 0x35,
	0x35, 0xff,
	0x3a, 0x00,
	0x37, 0x10,
	0x38, 0x10,
	0x39, 0x02,
	0x42, 0x60,
	0x4a, 0x80,
	0x4b, 0x04,
	0x4d, 0x81,
	0x5d, 0x88,
	0x50, 0x36,
	0x51, 0x36,
	0x52, 0x36,
	0x53, 0x36,
	0x63, 0x60,
	0x64, 0x10,
	0x65, 0x10,
	0x68, 0x04,
	0x69, 0x29,
	0x70, 0x20,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x40,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x60,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x80,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0xa0,
	0x71, 0x70,
	0x72, 0x04,
	0x73, 0x00,
	0x70, 0x1f,
	0xa0, 0x44,
	0xc0, 0x08,
	0xc1, 0x10,
	0xc2, 0x08,
	0xc3, 0x10,
	0xc4, 0x08,
	0xc5, 0xf0,
	0xc6, 0xf0,
	0xc7, 0x0a,
	0xc8, 0x1a,
	0xc9, 0x80,
	0xca, 0x23,
	0xcb, 0x24,
	0xce, 0x74,
	0x90, 0x03,
	0x76, 0x80,
	0x77, 0x42,
	0x78, 0x0a,
	0x79, 0x80,
	0xad, 0x40,
	0xae, 0x07,
	0x7f, 0xd4,
	0x7c, 0x00,
	0x80, 0xa8,
	0x81, 0xda,
	0x7c, 0x01,
	0x80, 0xda,
	0x81, 0xec,
	0x7c, 0x02,
	0x80, 0xca,
	0x81, 0xeb,
	0x7c, 0x03,
	0x80, 0xba,
	0x81, 0xdb,
	0x85, 0x08,
	0x86, 0x00,
	0x87, 0x02,
	0x89, 0x80,
	0x8b, 0x44,
	0x8c, 0xaa,
	0x8a, 0x10,
	0xba, 0x00,
	0xf5, 0x04,
	0xfe, 0x44,
	0xd2, 0x32,
	0xb8, 0x00,
	#else
    0x23, 0x0f,
    0x08, 0x07,
    0x0c, 0x00,
    0x21, 0x54,
    0x25, 0x82,
    0x27, 0x31,
    0x30, 0x08,
    0x31, 0x32,
    0x32, 0x32,
    0x33, 0x35,
    0x35, 0xff,
    0x3a, 0x00,
    0x37, 0x10,
    0x38, 0x10,
    0x39, 0x02,
    0x42, 0x60,
    0x4a, 0x80,
    0x4b, 0x04,
    0x4d, 0x81,
    0x5d, 0x88,
    0x50, 0x36,
    0x51, 0x36,
    0x52, 0x36,
    0x53, 0x36,
    0x63, 0x60,
    0x64, 0x10,
    0x65, 0x10,
    0x68, 0x04,
    0x69, 0x29,
    0x70, 0x20,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x40,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x60,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x80,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0xa0,
    0x71, 0x70,
    0x72, 0x04,
    0x73, 0x00,
    0x70, 0x1f,
    0xa0, 0x44,
    0xc0, 0x08,
    0xc1, 0x10,
    0xc2, 0x08,
    0xc3, 0x10,
    0xc4, 0x08,
    0xc5, 0xf0,
    0xc6, 0xf0,
    0xc7, 0x0a,
    0xc8, 0x1a,
    0xc9, 0x80,
    0xca, 0x23,
    0xcb, 0x24,
    0xce, 0x74,
    0x56, 0x01,
    0x90, 0x03,
    0x76, 0x80,
    0x77, 0x42,
    0x78, 0x0a,
    0x79, 0x80,
    0xad, 0x40,
    0xae, 0x07,
    0x7f, 0xd4,
    0x7c, 0x00,
    0x80, 0xa8,
    0x81, 0xda,
    0x7c, 0x01,
    0x80, 0xda,
    0x81, 0xec,
    0x7c, 0x02,
    0x80, 0xca,
    0x81, 0xeb,
    0x7c, 0x03,
    0x80, 0xba,
    0x81, 0xdb,
    0x85, 0x08,
    0x86, 0x00,
    0x87, 0x02,
    0x89, 0x80,
    0x8b, 0x44,
    0x8c, 0xaa,
    0x8a, 0x10,
    0xba, 0x00,
    0xf5, 0x04,
    0xfe, 0x44,
    0xd2, 0x32,
    0xb8, 0x00,
	#endif
};

/* DS3000 doesn't need some parameters as input and auto-detects them */
/* save input from the application of those parameters */
struct ds3000_tuning {
	u32 frequency;
	u32 symbol_rate;
	fe_spectral_inversion_t inversion;
	enum fe_code_rate fec;

	/* input values */
	u8 inversion_val;
	fe_modulation_t delivery;
	u8 rolloff;
};

struct ds3000_state {
	struct i2c_adapter *i2c;
	const struct ds3000_config *config;

	struct dvb_frontend frontend;

	struct ds3000_tuning dcur;
	struct ds3000_tuning dnxt;

	u8 skip_fw_load;

	/* previous uncorrected block counter for DVB-S2 */
	u16 prevUCBS2;
};

static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
{
	u8 buf[] = { reg, data };
	struct i2c_msg msg = { .addr = state->config->demod_address,
		.flags = 0, .buf = buf, .len = 2 };
	int err;

	dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);

	err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
			 " value == 0x%02x)\n", __func__, err, reg, data);
		return -EREMOTEIO;
	}

	return 0;
}

static int ds3000_readreg(struct ds3000_state *state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = {
		{
			.addr = state->config->demod_address,
			.flags = 0,
			.buf = b0,
			.len = 1
		}, {
			.addr = state->config->demod_address,
			.flags = I2C_M_RD,
			.buf = b1,
			.len = 1
		}
	};

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
		return ret;
	}

	dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);

	return b1[0];
}

static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
{
	u8 buf[] = { reg, data };
	struct i2c_msg msg = { .addr = 0x60,
		.flags = 0, .buf = buf, .len = 2 };
	int err;
	// qwm add at 2010.4.13
	u8 val;

	dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
	
	// qwm add at 2010.4.13
	val = ds3000_readreg(state, 0x03);
	val &= 0xf8;
	val |= 0x11;

	ds3000_writereg(state, 0x03, val); //0x11);
	err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk("%s: writereg error(err == %i, reg == 0x%02x,"
			 " value == 0x%02x)\n", __func__, err, reg, data);
		return -EREMOTEIO;
	}

	return 0;
}

/* I2C write for 8k firmware load */
static int ds3000_writeFW(struct ds3000_state *state, int reg,
				const u8 *data, u16 len)
{
	int i, ret = -EREMOTEIO;
	struct i2c_msg msg;
	u8 *buf;

	buf = kmalloc(3, GFP_KERNEL);
	if (buf == NULL) {
		printk(KERN_ERR "Unable to kmalloc\n");
		ret = -ENOMEM;
		goto error;
	}

	*(buf) = reg;

	msg.addr = state->config->demod_address;
	msg.flags = 0;
	msg.buf = buf;
	msg.len = 3;

	for (i = 0; i < len; i += 2) {
		memcpy(buf + 1, data + i, 2);

		dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);

		ret = i2c_transfer(state->i2c, &msg, 1);
		if (ret != 1) {
			printk(KERN_ERR "%s: write error(err == %i, "
				"reg == 0x%02x\n", __func__, ret, reg);
			ret = -EREMOTEIO;
		}
	}

error:
	kfree(buf);

	return ret;
}

static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = {
		{
			.addr = 0x60,
			.flags = 0,
			.buf = b0,
			.len = 1
		}, {
			.addr = 0x60,
			.flags = I2C_M_RD,
			.buf = b1,
			.len = 1
		}
	};
	// qwm add at 2010.4.13
	u8 val;

	val = ds3000_readreg(state, 0x03);
	val &= 0xf8;
	val |= 0x11;

	ds3000_writereg(state, 0x03, val); //0x12);
	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
		return ret;
	}

	dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);

	return b1[0];
}

static int ds3000_set_inversion(struct ds3000_state *state,
					fe_spectral_inversion_t inversion)
{
	dprintk("%s(%d)\n", __func__, inversion);

	switch (inversion) {
	case INVERSION_OFF:
	case INVERSION_ON:
	case INVERSION_AUTO:
		break;
	default:
		return -EINVAL;
	}

	state->dnxt.inversion = inversion;

	return 0;
}

static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
{
	int ret = 0;

	// qwm modified at 2010.4.14
#if 0
	dprintk("%s()\n", __func__);

	dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);

	/*  check if symbol rate is within limits */
	if ((state->dnxt.symbol_rate >
				state->frontend.ops.info.symbol_rate_max) ||
	    (state->dnxt.symbol_rate <
				state->frontend.ops.info.symbol_rate_min))
		ret = -EOPNOTSUPP;

	state->dnxt.symbol_rate = rate;
#else
	u32	tmp;
	u8	reg_0x61, reg_0x62;

	printk("%s() symbol_rate = %d\n", __func__, rate);
	tmp = (u32)((((rate/1000) << 15) + (DS3000_SAMPLE_RATE / 4)) / (DS3000_SAMPLE_RATE / 2));


	reg_0x61 = (u8)(tmp & 0x00FF);
	reg_0x62 = (u8)((tmp & 0xFF00) >> 8);

	ds3000_writereg(state, 0x61, reg_0x61);
	ds3000_writereg(state, 0x62, reg_0x62);
	
	state->dnxt.symbol_rate = rate;
#endif

	return ret;
}

// qwm add at 2010.4.19
static int ds3000_soft_reset(struct ds3000_state *state)
{
	g_cci_detect	 	= 1;
	g_auto_tune_cnt	 	= 0;

	ds3000_writereg(state, 0xb2, 0x01);
	ds3000_writereg(state, 0x00, 0x01);
	msleep(1);
	ds3000_writereg(state, 0x00, 0x00);
	ds3000_writereg(state, 0xb2, 0x00);

	return 0;
}

static int ds3000_hard_reset(struct ds3000_state *state)
{
	u8 val;

	val = ds3000_readreg(state, 0x08);
	val |= 0x01;
	ds3000_writereg(state, 0x08, val);


	/* reset global defines*/
	//g_current_type 		= MtFeType_DvbS;
	//g_connect_type 		= MtFeType_DvbS;
	//g_connect_sym_rate 	= 0;
	g_auto_tune_cnt    	= 0;
	g_cci_detect	   	= 0;

	
	msleep(1);
	
	return 0;
}

static int ds3000_load_firmware(struct dvb_frontend *fe,
					const struct firmware *fw);

static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	const struct firmware *fw;
	int ret = 0;

	dprintk("%s()\n", __func__);
	
	// qwm add at 2010.4.21
	if (g_load_firmware != 0)
		return 0;

	if (ds3000_readreg(state, 0xb2) <= 0)
		return ret;

	if (state->skip_fw_load)
		return 0;
	/* Load firmware */
	/* request the firmware, this will block until someone uploads it */
	printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
				DS3000_DEFAULT_FIRMWARE);
	ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
				state->i2c->dev.parent);
	printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
	if (ret) {
		printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
				"found?)\n", __func__);
		return ret;
	}

	/* Make sure we don't recurse back through here during loading */
	state->skip_fw_load = 1;

	ret = ds3000_load_firmware(fe, fw);
	if (ret)
		printk("%s: Writing firmware to device failed\n", __func__);

	release_firmware(fw);
	

	dprintk("%s: Firmware upload %s\n", __func__,
			ret == 0 ? "complete" : "failed");

	/* Ensure firmware is always loaded if required */
	state->skip_fw_load = 0;

	return ret;
}

// qwm add at 2010.4.9
#define FW_DOWN_SIZE	32
#define FW_DOWN_LOOP	(8192/FW_DOWN_SIZE)

static int ds3000_load_firmware(struct dvb_frontend *fe,
					const struct firmware *fw)
{
	struct ds3000_state *state = fe->demodulator_priv;
	u32 i;
	u8 *pbuf = (u8*)fw->data;

	dprintk("%s\n", __func__);
	dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
			fw->size,
			fw->data[0],
			fw->data[1],
			fw->data[fw->size - 2],
			fw->data[fw->size - 1]);

	/* Begin the firmware load process */
	ds3000_writereg(state, 0xb2, 0x01);
	/* write the entire firmware */
	// qwm add at 2010.49
	//ds3000_writeFW(state, 0xb0, fw->data, fw->size);
	for (i = 0; i < FW_DOWN_LOOP; i++)
	{
		ds3000_writeFW(state, 0xb0, &(pbuf[FW_DOWN_SIZE*i]), FW_DOWN_SIZE);
	}
	
	ds3000_writereg(state, 0xb2, 0x00);

	return 0;
}

static void ds3000_dump_registers(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	int x, y, reg = 0, val;

	for (y = 0; y < 16; y++) {
		dprintk("%s: %02x: ", __func__, y);
		for (x = 0; x < 16; x++) {
			reg = (y << 4) + x;
			val = ds3000_readreg(state, reg);
			if (x != 15)
				dprintk("%02x ",  val);
			else
				dprintk("%02x\n", val);
		}
	}
	dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
}

// qwm add at 2010.4.12
static int ds3000_set_CCI(struct ds3000_state *state, u32 is_cci_on)
{
	u8 tmp;

	tmp = ds3000_readreg(state, 0x56);
	if (is_cci_on == 0) //MtFe_On)
		tmp &= ~0x01;
	else
		tmp |= 0x01;
	ds3000_writereg(state, 0x56, tmp);

	return 0;
}

static int ds3000_check_CCI(struct ds3000_state *state, u32 *p_state)
{
	u8 i, cnt, reg_0xb3, reg_0x59, CCI_on_flag_cnt;
	s8 val_cci;
	
	cnt = 0;

	reg_0xb3 = ds3000_readreg(state, 0xb3);
	while((reg_0xb3 == 0x38)||(reg_0xb3 <= 3))
	{
		cnt ++;
		if (cnt > 10)
		{
			*p_state = 2;	// unlock
			return 0;
		}
		msleep(10);
		reg_0xb3 = ds3000_readreg(state, 0xb3);
	}


	CCI_on_flag_cnt = 0;
	for(i = 0; i < 15; i++)
	{
		reg_0x59 = ds3000_readreg(state, 0x59);
		val_cci = (s8)reg_0x59;
		
		if(val_cci < 0)
		{
			CCI_on_flag_cnt = 0;
			break;
		}

		if(val_cci > 2)	//MT_FE_CCI_THRESHOLD
			CCI_on_flag_cnt++;
	}


	if (CCI_on_flag_cnt < 10)
		ds3000_set_CCI(state, 0);	// MtFe_Off


	msleep(1);
	
	return 0;
}

static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int lock;
	
	// qwm add at 2010.4.19
	fe_status_t ftmp;
	u8 tmp;
	u32 pStatus = 0;

	if(g_cci_detect == 1)
	{
		ds3000_check_CCI(state, &pStatus);			

		if(pStatus == 2) //MtFeLockState_Unlocked)
			return 0;

		g_cci_detect = 0;
	}
	// end qwm add

	*status = 0;

	switch (c->delivery_system) {
	case SYS_DVBS:
		lock = ds3000_readreg(state, 0xd1);
		if ((lock & 0x07) == 0x07)
			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
				FE_HAS_VITERBI | FE_HAS_SYNC |
				FE_HAS_LOCK;

		break;
	case SYS_DVBS2:
		lock = ds3000_readreg(state, 0x0d);
		if ((lock & 0x8f) == 0x8f)
			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
				FE_HAS_VITERBI | FE_HAS_SYNC |
				FE_HAS_LOCK;

		break;
	default:
		return 1;
	}
	#ifdef __QWM_DGB__
	// qwm add at 2010.4.9
	printk("%s(%d)lock = 0x%02X\n", __func__, __LINE__, lock);
	#endif
	dprintk("%s: status = 0x%02x\n", __func__, lock);

	// qwm add at 2010.4.19
	ftmp = FE_HAS_SIGNAL | FE_HAS_CARRIER |
				FE_HAS_VITERBI | FE_HAS_SYNC |
				FE_HAS_LOCK;
	if (*status == ftmp)
	{
		return 0;
	}
	
	tmp = ds3000_readreg(state, 0xb3);
	if (!(c->delivery_system == SYS_DVBS || c->delivery_system == SYS_DVBS2))
	//MtFeType_DvbS_Unknown
	{
		if ((tmp & 0xc0) != 0)
		{
			*status = 0;
			return 0;
		}
	}
	else
	{
		if((tmp & 0x80) == 0x80)
		{
			*status = 0;
			return 0;
		}
		
		
		if((tmp & 0x40) == 0x40)
		{
			if(g_auto_tune_cnt < 2)
			{
				ds3000_set_demod(fe);
			}
			else
			{
				*status = 0;
				return 0;
			}
		}
	}

	return 0;
}

#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
static int ds3000_is_tuned(struct dvb_frontend *fe)
{
	fe_status_t tunerstat;

	ds3000_read_status(fe, &tunerstat);

	return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
}

/* read DS3000 BER value */
static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	u8 data;
	u32 ber_reading, lpdc_frames;

	dprintk("%s()\n", __func__);

	switch (c->delivery_system) {
	case SYS_DVBS:
		/* set the number of bytes checked during
		BER estimation */
		ds3000_writereg(state, 0xf9, 0x04);
		/* read BER estimation status */
		data = ds3000_readreg(state, 0xf8);
		/* check if BER estimation is ready */
		if ((data & 0x10) == 0) {
			/* this is the number of error bits,
			to calculate the bit error rate
			divide to 8388608 */
			*ber = (ds3000_readreg(state, 0xf7) << 8) |
				ds3000_readreg(state, 0xf6);
			/* start counting error bits */
			/* need to be set twice
			otherwise it fails sometimes */
			data |= 0x10;
			ds3000_writereg(state, 0xf8, data);
			ds3000_writereg(state, 0xf8, data);
		} else
			/* used to indicate that BER estimation
			is not ready, i.e. BER is unknown */
			*ber = 0xffffffff;
		break;
	case SYS_DVBS2:
		/* read the number of LPDC decoded frames */
		lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
				(ds3000_readreg(state, 0xd6) << 8) |
				ds3000_readreg(state, 0xd5);
		/* read the number of packets with bad CRC */
		ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
				ds3000_readreg(state, 0xf7);
		if (lpdc_frames > 3000) { //750) {        qwm modified at 2010.4.23
			/* clear LPDC frame counters */
			ds3000_writereg(state, 0xd1, 0x01);
			/* clear bad packets counter */
			ds3000_writereg(state, 0xf9, 0x01);
			/* enable bad packets counter */
			ds3000_writereg(state, 0xf9, 0x00);
			/* enable LPDC frame counters */
			ds3000_writereg(state, 0xd1, 0x00);
			*ber = ber_reading;
		} else
			/* used to indicate that BER estimation is not ready,
			i.e. BER is unknown */
			*ber = 0xffffffff;
		break;
	default:
		return 1;
	}

	return 0;
}

/* read TS2020 signal strength */
static int ds3000_read_signal_strength(struct dvb_frontend *fe,
						u16 *signal_strength)
{
	struct ds3000_state *state = fe->demodulator_priv;
	u16 sig_reading, sig_strength;
	u8 rfgain, bbgain;
	u8  	strength, AgcPWM;
	u16 	gain,Vagc, vagctmp;

	dprintk("%s()\n", __func__);
	
	// qwm add at 2010.4.12
	
	// Step 1: read the AGC PWM rate from the demodulator register
	AgcPWM = ds3000_readreg(state, 0x3f);
#ifdef __QWM_DGB__
	printk("%s(%d)AgcPWM = %d\n", __func__, __LINE__, AgcPWM);
#endif
	
	// Step 2: Calculate the AGC voltage based on the AGC PWM rate
	Vagc = AgcPWM * 20 - 1166;					//Convert the AGC PWM rate to AGC Voltage,unit: mV
#ifdef __QWM_DGB__
	printk("%s(%d)Vagc = %d\n", __func__, __LINE__, Vagc);
#endif

	// Step 3: Calculate the total gain of the tuner
	rfgain = ds3000_tuner_readreg(state, 0x3d);// & 0x1f;
	bbgain = ds3000_tuner_readreg(state, 0x21);// & 0x1f;
#ifdef __QWM_DGB__
	printk("%s(%d)rfgain = %d\n", __func__, __LINE__, rfgain);
	printk("%s(%d)bbgain = %d\n", __func__, __LINE__, bbgain);
#endif
	rfgain &= 0x1f;
	bbgain &= 0x1f;

	if (rfgain < 0)			// qwm add
		rfgain = 0;
	if (rfgain > 15)
		rfgain = 15;
	if (bbgain < 0)			// qwm add
		bbgain = 0;
	if (bbgain > 13)
		bbgain = 13;
	
	// qwm add
	vagctmp = Vagc;
	if(vagctmp < 400)		 vagctmp = 400;     
	if(vagctmp > 1100)      vagctmp = 1100;
	
	gain = (u16) rfgain * 233 + (u16) bbgain * 350 + vagctmp * 24 / 10;
#ifdef __QWM_DGB__
	printk("%s(%d)gain = %d\n", __func__, __LINE__, gain);
#endif
	
	// Step 4: Calculate the signal strength based on the total gain of the tuner
	if(gain > 7300)			strength =  0;							    //0%           no signal or weak signal
	else if(gain > 5800)	strength = 0 + (7300 - gain)  * 13 / 300;	//0% - 65%     weak signal
	else if(gain > 4200)	strength = 65 + (5800 - gain) * 1 / 80;		//65% - 85%    normal signal
	else					strength = 85 + (4200 - gain) * 3 / 580;	//85% - 100%   strong signal
#ifdef __QWM_DGB__
	printk("%s(%d)strength = %d\n", __func__, __LINE__, strength);
#endif


	sig_reading = rfgain * 2 + bbgain * 3;

	sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;

	/* cook the value to be suitable for szap-s2 human readable output */
	*signal_strength = sig_strength * 1000;

	#ifdef __QWM_DGB__
	// qwm add at 2010.4.9
	printk("%s(%d)strength = %d\n", __func__, __LINE__, strength);
	printk("%s(%d)raw / cooked = 0x%04x / 0x%04x\n", __func__, __LINE__, sig_reading, *signal_strength);
	*signal_strength = strength;
	#endif
	dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
			sig_reading, *signal_strength);

	return 0;
}

/* calculate DS3000 snr value in dB */
static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	u8 snr_reading, snr_value;
	u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
	static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
		0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
		0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
		0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
	};
	static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
		0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
		0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
		0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
		0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
		0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
		0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
		0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
		0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
		0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
		0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
		0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
		0x49e9, 0x4a20, 0x4a57
	};

	dprintk("%s()\n", __func__);

	switch (c->delivery_system) {
	case SYS_DVBS:
		snr_reading = ds3000_readreg(state, 0xff);
		#ifdef __QWM_DGB__
		// qwm add at 2010.4.9
		printk("%s(%d)read 0xff = 0x%02x\n", __func__, __LINE__, snr_reading);
		#endif
		snr_reading /= 8;
		if (snr_reading == 0)
			*snr = 0x0000;
		else {
			if (snr_reading > 20)
				snr_reading = 20;
			snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
			/* cook the value to be suitable for szap-s2
			human readable output */
			*snr = snr_value * 8 * 655;
		}
		#ifdef __QWM_DGB__
		// qwm add at 2010.4.9
		printk("%s(%d) raw / cooked = 0x%02x / 0x%04x\n", __func__, __LINE__,
				snr_reading, *snr);
		#endif
		dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
				snr_reading, *snr);
		break;
	case SYS_DVBS2:
		dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
				(ds3000_readreg(state, 0x8d) << 4);
		#ifdef __QWM_DGB__
		// qwm add at 2010.4.9
		printk("%s(%d)read dvbs2_noise_reading = 0x%02x\n", __func__, __LINE__, dvbs2_noise_reading);
		#endif
		dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
		tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
		if (dvbs2_signal_reading == 0) {
			*snr = 0x0000;
			return 0;
		}
		if (dvbs2_noise_reading == 0) {
			snr_value = 0x0013;
			/* cook the value to be suitable for szap-s2
			human readable output */
			*snr = 0xffff;
			return 0;
		}
		if (tmp > dvbs2_noise_reading) {
			snr_reading = tmp / dvbs2_noise_reading;
			if (snr_reading > 80)
				snr_reading = 80;
			snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
			/* cook the value to be suitable for szap-s2
			human readable output */
			*snr = snr_value * 5 * 655;
		} else {
			snr_reading = dvbs2_noise_reading / tmp;
			if (snr_reading > 80)
				snr_reading = 80;
			*snr = -(dvbs2_snr_tab[snr_reading] / 1000);
		}
		dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
				snr_reading, *snr);
		break;
	default:
		return 1;
	}
	#ifdef __QWM_DGB__
	// qwm add at 2010.4.9
	printk("%s(%d)SNR = %d\n", __func__, __LINE__, *snr);
	#endif

	return 0;
}

/* read DS3000 uncorrected blocks */
static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	u8 data;
	u16 _ucblocks;

#ifdef __QWM_DGB__
	printk("%s(%d)*******************\n", __func__, __LINE__);
#endif
	dprintk("%s()\n", __func__);

	switch (c->delivery_system) {
	case SYS_DVBS:
		*ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
				ds3000_readreg(state, 0xf4);
		data = ds3000_readreg(state, 0xf8);
		/* clear packet counters */
		data &= ~0x20;
		ds3000_writereg(state, 0xf8, data);
		/* enable packet counters */
		data |= 0x20;
		ds3000_writereg(state, 0xf8, data);
		break;
	case SYS_DVBS2:
		_ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
				ds3000_readreg(state, 0xe1);
		if (_ucblocks > state->prevUCBS2)
			*ucblocks = _ucblocks - state->prevUCBS2;
		else
			*ucblocks = state->prevUCBS2 - _ucblocks;
		state->prevUCBS2 = _ucblocks;
		break;
	default:
		return 1;
	}

	return 0;
}

/* Overwrite the current tuning params, we are about to tune */
static void ds3000_clone_params(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
}

static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
{
	struct ds3000_state *state = fe->demodulator_priv;
		u8 data;

	// qwm add at 2010.4.20
	//struct dvb_frontend_properties *prop = fe->dtv_property_cache;
	u8 val_0xa1, val_0xa2;
#ifdef __QWM_DGB__
	printk("%s(%d)*********tone = %d\n", __func__, __LINE__, tone);
#endif

#if 0
	dprintk("%s(%d)\n", __func__, tone);
	if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
		printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
		return -EINVAL;
	}

	data = ds3000_readreg(state, 0xa2);
	data &= ~0xc0;
	ds3000_writereg(state, 0xa2, data);

	switch (tone) {
	case SEC_TONE_ON:
		dprintk("%s: setting tone on\n", __func__);
		data = ds3000_readreg(state, 0xa1);
		data &= ~0x43;
		data |= 0x04;
		ds3000_writereg(state, 0xa1, data);
		break;
	case SEC_TONE_OFF:
		dprintk("%s: setting tone off\n", __func__);
		data = ds3000_readreg(state, 0xa2);
		data |= 0x80;
		ds3000_writereg(state, 0xa2, data);
		break;
	}
#else
	val_0xa1 = ds3000_readreg(state, 0xa1);
	val_0xa2 = ds3000_readreg(state, 0xa2);
	/*if (tone == SEC_TONE_OFF)
	{
		val_0xa1 |= 0x40;
		val_0xa2 |= 0x02;	//LNB_ENABLE_WHEN_LNB_EN_HIGH 0
		val_0xa2 |= 0x01;	//LNB_VSEL_STANDBY_HIGH 1
		val_0xa2 &= ~0xc0;	//LNB_DISEQC_OUT_FORCE_HIGH 0
		val_0xa2 |= 0x80;
	}
	else if (tone == SEC_TONE_ON)
	{
		val_0xa2 &= ~0x02;	//LNB_ENABLE_WHEN_LNB_EN_HIGH 0
		if (prop->voltage == SEC_VOLTAGE_13)	//LNB_13V_WHEN_VSEL_HIGH 1
			val_0xa2 |= 0x01;
		else
			val_0xa2 &= ~0x01;
	}*/
	if (tone == SEC_TONE_ON)
	{
		val_0xa1 |= 0x04;
		val_0xa1 &= ~0x03;
		val_0xa1 &= ~0x40;
		val_0xa2 &= ~0xc0;
	}
	else
	{
		val_0xa2 &= ~0xc0;		// LNB_DISEQC_OUT_FORCE_HIGH 0
		val_0xa2 |= 0x80;
	}
	ds3000_writereg(state, 0xa2, val_0xa2);
	ds3000_writereg(state, 0xa1, val_0xa1);
#endif

#ifdef __QWM_DGB__
	data = ds3000_readreg(state, 0xa1);
	printk("%s(%d)0xa1 = 0x%02x\n", __func__, __LINE__, data);
	data = ds3000_readreg(state, 0xa2);
	printk("%s(%d)0xa2 = 0x%02x\n", __func__, __LINE__, data);
#endif


	return 0;
}

static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
				struct dvb_diseqc_master_cmd *d)
{
	struct ds3000_state *state = fe->demodulator_priv;
	int i;
	u8 data;

	/* Dump DiSEqC message */
#ifdef __QWM_DGB__
	printk("%s																																																																																										(%d)*********\n", __func__, __LINE__);
	printk("%s(%d)", __func__, __LINE__);
	for (i = 0 ; i < d->msg_len;) {
		printk("0x%02x", d->msg[i]);
		if (++i < d->msg_len)
			printk(", ");
	}
#endif

	/* enable DiSEqC message send pin */
	data = ds3000_readreg(state, 0xa2);
	data &= ~0xc0;
	ds3000_writereg(state, 0xa2, data);

	/* DiSEqC message */
	for (i = 0; i < d->msg_len; i++)
		ds3000_writereg(state, 0xa3 + i, d->msg[i]);

	data = ds3000_readreg(state, 0xa1);
#if 0
	/* clear DiSEqC message length and status,
	enable DiSEqC message send */
	data &= ~0xf8;
	/* set DiSEqC mode, modulation active during 33 pulses,
	set DiSEqC message length */
	data |= ((d->msg_len - 1) << 3) | 0x07;
#else
	data &= ~0x38;
	data &= ~0x40;
	data |= ((d->msg_len-1) << 3) | 0x07;
	//if (d->msg->is_enable_receive)
	//	data |= 0x80;
	//else
		data &= ~0x80;
#endif
	ds3000_writereg(state, 0xa1, data);

	/* wait up to 150ms for DiSEqC transmission to complete */
	for (i = 0; i < 15; i++) {
		data = ds3000_readreg(state, 0xa1);
		if ((data & 0x40) == 0)
			break;
		msleep(10);
	}

	/* DiSEqC timeout after 150ms */
	if (i == 15) {
		data = ds3000_readreg(state, 0xa1);
		data &= ~0x80;
		data |= 0x40;
		ds3000_writereg(state, 0xa1, data);

		data = ds3000_readreg(state, 0xa2);
		data &= ~0xc0;		//LNB_DISEQC_OUT_FORCE_HIGH 0
		data |= 0x80;
		ds3000_writereg(state, 0xa2, data);

		return 1;
	}

	data = ds3000_readreg(state, 0xa2);
	data &= ~0xc0;
	data |= 0x80;
	ds3000_writereg(state, 0xa2, data);
#ifdef __QWM_DGB__
	data = ds3000_readreg(state, 0xa1);
	printk("%s(%d)0xa1 = 0x%02x\n", __func__, __LINE__, data);
	data = ds3000_readreg(state, 0xa2);
	printk("%s(%d)0xa2 = 0x%02x\n", __func__, __LINE__, data);
#endif

	return 0;
}

/* Send DiSEqC burst */
static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
					fe_sec_mini_cmd_t burst)
{
	struct ds3000_state *state = fe->demodulator_priv;
	int i;
	u8 data;

#ifdef __QWM_DGB__
	printk("%s(%d)*********\n", __func__, __LINE__);
#endif
	dprintk("%s()\n", __func__);

	data = ds3000_readreg(state, 0xa2);
	data &= ~0xc0;
	ds3000_writereg(state, 0xa2, data);

	/* DiSEqC burst */
	if (burst == SEC_MINI_A)
		/* Unmodulated tone burst */
		ds3000_writereg(state, 0xa1, 0x02);
	else if (burst == SEC_MINI_B)
		/* Modulated tone burst */
		ds3000_writereg(state, 0xa1, 0x01);
	else
		return -EINVAL;

	msleep(13);
	for (i = 0; i < 5; i++) {
		data = ds3000_readreg(state, 0xa1);
		if ((data & 0x40) == 0)
			break;
		msleep(1);
	}

	// qwm annotate at 2010.4.20
	/*
	if (i == 5) {
		data = ds3000_readreg(state, 0xa1);
		data &= ~0x80;
		data |= 0x40;
		ds3000_writereg(state, 0xa1, data);

		data = ds3000_readreg(state, 0xa2);
		data &= ~0xc0;
		data |= 0x80;
		ds3000_writereg(state, 0xa2, data);

		return 1;
	}
	*/

	data = ds3000_readreg(state, 0xa2);
	data &= ~0xc0;
	data |= 0x80;
	ds3000_writereg(state, 0xa2, data);

#ifdef __QWM_DGB__
	data = ds3000_readreg(state, 0xa1);
	printk("%s(%d)0xa1 = 0x%02x\n", __func__, __LINE__, data);
	data = ds3000_readreg(state, 0xa2);
	printk("%s(%d)0xa2 = 0x%02x\n", __func__, __LINE__, data);
#endif

	return 0;
}

// qwm add at 2010.4.21
static int ds3000_set_LNB(struct ds3000_state *state, 
	s32 is_LNB_enable, s32 is_22k_enable, fe_sec_voltage_t voltage_type)
{
	u8	val_0xa1, val_0xa2;

	val_0xa1 = ds3000_readreg(state, 0xa1);
	val_0xa2 = ds3000_readreg(state, 0xa2);
#ifdef __QWM_DGB__
	printk("%s(%d)get 0xa1 = 0x%02X\n", __func__, __LINE__, val_0xa1);
	printk("%s(%d)get 0xa2 = 0x%02X\n", __func__, __LINE__, val_0xa2);
#endif

	if(is_LNB_enable != 1)
	{
		val_0xa1 |= 0x40;
		
		/*set LNB_EN pin HIGH or LOW */
		#if 0 //(LNB_ENABLE_WHEN_LNB_EN_HIGH)
			val_0xa2 &= ~0x02;
		#else
			val_0xa2 |= 0x02;
		#endif


		/*set V_SEL Pin mode*/
		#if 1 //(LNB_VSEL_STANDBY_HIGH)
			val_0xa2 |= 0x01;
		#else
			val_0xa2 &= ~0x01;
		#endif


		/*set DiseQc_OUT mode*/
		#if 0 //(LNB_DISEQC_OUT_FORCE_HIGH)
			val_0xa2 |= 0xc0;
		#else
			val_0xa2 &= ~0xc0;
			val_0xa2 |= 0x80;
		#endif
	}
	else
	{
		#if 0 //(LNB_ENABLE_WHEN_LNB_EN_HIGH)
			val_0xa2 |= 0x02;
		#else
			val_0xa2 &= ~0x02;
		#endif


		#if 1 //(LNB_13V_WHEN_VSEL_HIGH)
			if (voltage_type == SEC_VOLTAGE_13)
				val_0xa2 |= 0x01;
			else
				val_0xa2 &= ~0x01;
		#else
			if (voltage_type == MtFeLNB_13V)
				val_0xa2 &= ~0x01;
			else
				val_0xa2 |= 0x01;
		#endif


		if (is_22k_enable == 1) //MtFe_True)
		{
			val_0xa1 |= 0x04;
			val_0xa1 &= ~0x03;
			val_0xa1 &= ~0x40;
			val_0xa2 &= ~0xc0;
		}
		else
		{
			#if 0 //(LNB_DISEQC_OUT_FORCE_HIGH)
				val_0xa2 |= 0xc0;
			#else
				val_0xa2 &= ~0xc0;
				val_0xa2 |= 0x80;
			#endif
		}
	}

	ds3000_writereg(state, 0xa2, val_0xa2);
	ds3000_writereg(state, 0xa1, val_0xa1);

#ifdef __QWM_DGB__
	printk("%s(%d) 0xa1 = 0x%02X\n", __func__, __LINE__, val_0xa1);
	printk("%s(%d) 0xa2 = 0x%02X\n", __func__, __LINE__, val_0xa2);
#endif

	return 0;
}

static void ds3000_release(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	dprintk("%s\n", __func__);
	
	// qwm add 2010.4.21
	ds3000_set_LNB(state, 0, 0, fe->dtv_property_cache.voltage);

	kfree(state);
}

static struct dvb_frontend_ops ds3000_ops;

struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
				    struct i2c_adapter *i2c)
{
	struct ds3000_state *state = NULL;
	int ret;

	dprintk("%s\n", __func__);
	
	// qwm add at 2010.4.19
	g_cci_detect = 0;

	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct ds3000_state), GFP_KERNEL);
	if (state == NULL) {
		printk(KERN_ERR "Unable to kmalloc\n");
		goto error2;
	}

	/* setup the state */
	memset(state, 0, sizeof(struct ds3000_state));

	state->config = config;
	state->i2c = i2c;
	state->prevUCBS2 = 0;

	/* check if the demod is present */
	ret = ds3000_readreg(state, 0x00) & 0xfe;
	if (ret != 0xe0) {
		printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
		goto error3;
	}

	printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
			ds3000_readreg(state, 0x02),
			ds3000_readreg(state, 0x01));

	memcpy(&state->frontend.ops, &ds3000_ops,
			sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error3:
	kfree(state);
error2:
	return NULL;
}
EXPORT_SYMBOL(ds3000_attach);

static int ds3000_set_property(struct dvb_frontend *fe,
	struct dtv_property *tvp)
{
#ifdef __QWM_DGB__
	printk("%s(%d)*******\n", __func__, __LINE__);
#endif
	dprintk("%s(..)\n", __func__);
	return 0;
}

static int ds3000_get_property(struct dvb_frontend *fe,
	struct dtv_property *tvp)
{
	dprintk("%s(..)\n", __func__);
	return 0;
}

// qwm add at 2010.4.12. Equal _mt_fe_dmd_ds3k_set_ts_out_mode
static int ds3000_set_ts_out(struct dvb_frontend *fe, int mode)
{
	struct ds3000_state *state = fe->demodulator_priv;
	u8 tmp, val_0x08, buf;
	
	val_0x08 = ds3000_readreg(state, 0x08);

	/*set DVBS mode*/
	tmp = (u8)(val_0x08 & (~0x04));
	ds3000_writereg(state, 0x08, tmp);
	
	tmp = ds3000_readreg(state, 0xfd);
	if (mode == 2)		//MtFeTsOutMode_Parallel
	{
		tmp &= ~0x80;
		tmp &= ~0x40;
	}
	else if (mode == 1)	// MtFeTsOutMode_Serial
	{
		tmp &= ~0x80;
		tmp |= 0x40;
	}
	else  // MtFeTsOutMode_Common
	{
		tmp |= 0x80;
		tmp &= ~0x40;
		
		tmp &= ~0x20;
	}
	ds3000_writereg(state, 0xfd, tmp);

	/*set DVBS2 mode*/
	tmp = (u8)(val_0x08|0x04);
	ds3000_writereg(state, 0x08, tmp);

	tmp = ds3000_readreg(state, 0xfd);
	if (mode == 2)		//MtFeTsOutMode_Parallel
	{
		tmp &= ~0x01;
		tmp &= ~0x04;
	}
	else if (mode == 1)	// MtFeTsOutMode_Serial
	{
		tmp &= ~0x01;
		tmp |= 0x04;
	}
	else  // MtFeTsOutMode_Common
	{
		tmp |= 0x01;
		tmp &= ~0x04;
		tmp &= ~0x40;
	}
	
	ds3000_writereg(state, 0xfd, tmp);
	
	ds3000_writereg(state, 0x08, val_0x08);

	#ifdef __QWM_DGB__
	buf = ds3000_tuner_readreg(state, 0x08);
	printk("%s(%d)tuner 0x08 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0xfd);
	printk("%s(%d)tuner 0xfd = 0x%02X\n", __func__, __LINE__, buf);
	#endif
	
	return 0;
}

// qwm add at 2010.4.19
static int ds3000_tuner_init(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	u8 buf;
	
	// qwm add at 2010.4.21
	//struct dtv_frontend_properties *cache = fe->dtv_property_cache;
	ds3000_set_LNB(state, 1, 1, fe->dtv_property_cache.voltage);

	/* TS2020 init */
	ds3000_tuner_writereg(state, 0x42, 0x63); //0x73);
	ds3000_tuner_writereg(state, 0x05, 0x01);
	// end modified
	ds3000_tuner_writereg(state, 0x62, 0xf5);

	#ifdef __QWM_DGB__
	buf = ds3000_tuner_readreg(state, 0x42);
	printk("%s(%d)tuner 0x42 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x05);
	printk("%s(%d)tuner 0x05 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x62);
	printk("%s(%d)tuner 0x62 = 0x%02X\n", __func__, __LINE__, buf);
	#endif

	return 0;
}

// qwm add at 2010.4.14
static s32 g_tuner_freq_offset_KHz;
static int ds3000_set_tuner(struct dvb_frontend *fe, u32 freq_KHz, u32 sym_rate_KSs, s16 lpf_offset_KHz)
{
	struct ds3000_state *state = fe->demodulator_priv;
	s32 g_tuner_freq_offset_KHz;
	u32 ndiv, f3db;
	u16     gdiv28;
	u8 div4, K, buf, /*buf2,*/ changePLL, value;	// qwm add at 2010.4.10
	u8 /*mlpf,*/ mlpf_new, mlpf_max, mlpf_min, nlpf;

	// equal 'mt_fe_tn_init_ts2020'
	ds3000_tuner_init(fe);

	ds3000_tuner_writereg(state, 0x07, 0x02);
	ds3000_tuner_writereg(state, 0x10, 0x00);
	ds3000_tuner_writereg(state, 0x60, 0x79);
	ds3000_tuner_writereg(state, 0x08, 0x01);
	ds3000_tuner_writereg(state, 0x00, 0x01);
	
	div4 = changePLL = 0;

	//  set the PLL
	K = (u8)((DS3000_XTAL_FREQ + 1000)/2000 - 8);
	#ifdef __QWM_DGB__
	printk("%s(%d)K = %d\n", __func__, __LINE__, K);
	#endif

	/* calculate and set freq divider */
	if (state->dcur.frequency < 1146000) {
		ds3000_tuner_writereg(state, 0x10, 0x11);
		// qwm add at 2010.4.9
		div4 = 1;
		//ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
		//		(DS3000_XTAL_FREQ / 2)) /
		//		DS3000_XTAL_FREQ - 1024;
		ndiv = ((state->dcur.frequency * (6/*PLL*/ + 8) * 8 /
				DS3000_XTAL_FREQ + 1) / 2) - 1024;
	} else {
		ds3000_tuner_writereg(state, 0x10, 0x01);
		// qwm add at 2010.4.9
		//ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
		//		(DS3000_XTAL_FREQ / 2)) /
		//		DS3000_XTAL_FREQ - 1024;
		ndiv = ((state->dcur.frequency * (6/*PLL*/ + 8) * 4 /
				DS3000_XTAL_FREQ + 1) / 2) - 1024;
	}
	// qwm debug tuner register
	#ifdef __QWM_DGB__
	printk("%s(%d)N = %d\n", __func__, __LINE__, ndiv);
	#endif

	buf = (ndiv >>8) & 0x0f;
	ds3000_tuner_writereg(state, 0x01, buf); //(ndiv & 0x0f00) >> 8);
	buf = ndiv & 0xff;
	ds3000_tuner_writereg(state, 0x02, buf); //ndiv & 0x00ff);

	/* set pll */
	buf = K;
	ds3000_tuner_writereg(state, 0x03, buf); //0x06);
	ds3000_tuner_writereg(state, 0x51, 0x0f);
	ds3000_tuner_writereg(state, 0x51, 0x1f);
	ds3000_tuner_writereg(state, 0x50, 0x10);
	ds3000_tuner_writereg(state, 0x50, 0x00);
	msleep(5);

	buf = ds3000_tuner_readreg(state, 0x66);
	changePLL = (((buf & 0x80) >> 7) != div4); 
	if(changePLL)
	{
		ds3000_tuner_writereg(state, 0x10, 0x11);

		div4 = 1;

		ndiv = (u32)((state->dcur.frequency * (K + 8) * 8 / DS3000_XTAL_FREQ + 1) / 2 - 1024);
		buf = (ndiv >>8) & 0x0f;
		ds3000_tuner_writereg(state, 0x01, buf);

		buf = ndiv & 0xff;
		ds3000_tuner_writereg(state, 0x02, buf); 

		ds3000_tuner_writereg(state, 0x51, 0x0f);
		ds3000_tuner_writereg(state, 0x51, 0x1f);  
		ds3000_tuner_writereg(state, 0x50, 0x10);
		ds3000_tuner_writereg(state, 0x50, 0x00);
		msleep(5);
	}

	ds3000_tuner_writereg(state, 0x51, 0x17);
	ds3000_tuner_writereg(state, 0x51, 0x1f);
	ds3000_tuner_writereg(state, 0x50, 0x08);
	ds3000_tuner_writereg(state, 0x50, 0x00);
	msleep(5);

	value = ds3000_tuner_readreg(state, 0x3d);
	//value &= 0x0f;
	if (value < 15) {
	//if ((value > 4) && (value < 15)) {
		value -= 3;
		if (value < 4)
			value = 4;
		value = ((value << 3) | 0x01) & 0x79;
		#ifdef __QWM_DGB__
		printk("%s(%d)buf < 15 0x60= 0x%02X\n", __func__, __LINE__, value);
		#endif
		// qwm modified at 2010.4.12
		ds3000_tuner_writereg(state, 0x60, value);
		ds3000_tuner_writereg(state, 0x51, 0x17);
		ds3000_tuner_writereg(state, 0x51, 0x1f);
		ds3000_tuner_writereg(state, 0x50, 0x08);
		ds3000_tuner_writereg(state, 0x50, 0x00);
	}

	f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
	if ((state->dcur.symbol_rate / 1000) < 5000)
		f3db += lpf_offset_KHz; //3000;
	if (f3db < 7000)
		f3db = 7000;
	if (f3db > 40000)
		f3db = 40000;
	// qwm debug tuner register
	#ifdef __QWM_DGB__
	printk("%s(%d)f3db = %d\n", __func__, __LINE__, f3db);
	#endif

	/* set low-pass filter period */
	gdiv28 = (u16)((DS3000_XTAL_FREQ * 1694 + 500 * 1000) / 1000000); 
	#ifdef __QWM_DGB__
	printk("%s(%d)gdiv28 = %d\n", __func__, __LINE__, gdiv28);
	#endif
	buf = (u8)gdiv28;
	ds3000_tuner_writereg(state, 0x04, buf); //0x2e);
	ds3000_tuner_writereg(state, 0x51, 0x1b);
	ds3000_tuner_writereg(state, 0x51, 0x1f);
	ds3000_tuner_writereg(state, 0x50, 0x04);
	ds3000_tuner_writereg(state, 0x50, 0x00);
	msleep(5);

	/* set low-pass filter baseband */
	value = ds3000_tuner_readreg(state, 0x26);
	gdiv28 = gdiv28 * 207 / ((value << 1) + 151);
	mlpf_max = gdiv28 * 135 / 100;
	mlpf_min = gdiv28 * 78 / 100;
	if (mlpf_max > 63)
		mlpf_max = 63;
	#ifdef __QWM_DGB__
	printk("%s(%d)mlpf_max = %d, mlpf_min = %d\n", __func__, __LINE__, mlpf_max, mlpf_min);
	#endif

	/* rounded to the closest integer */
	/*nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
			/ (2766 * DS3000_XTAL_FREQ);*/
	nlpf = ((gdiv28 * f3db * 2 * 1000 / 2766 / DS3000_XTAL_FREQ + 1)/ 2);
	if (nlpf > 23)
		nlpf = 23;
	if (nlpf < 1)
		nlpf = 1;
	#ifdef __QWM_DGB__
	printk("%s(%d)lpf_gm = %d\n", __func__, __LINE__, nlpf);
	#endif

	/* rounded to the closest integer */
	// qwm add at 2010.4.10
	/*mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
			(1000 * f3db / 2)) / (1000 * f3db);*/
	mlpf_new = ((nlpf * DS3000_XTAL_FREQ * 2766 * 2 / f3db / 1000 + 1) / 2);
	#ifdef __QWM_DGB__
	printk("%s(%d)lpf_mixdiv = %d\n", __func__, __LINE__, mlpf_new);
	#endif

	if (mlpf_new < mlpf_min) {
		nlpf++;
		// qwm add at 2010.4.10
		/*mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
				(1000 * f3db / 2)) / (1000 * f3db);*/
		mlpf_new = ((nlpf * DS3000_XTAL_FREQ * 2766 * 2/ f3db / 1000 + 1) / 2);
	}

	if (mlpf_new > mlpf_max)
		mlpf_new = mlpf_max;
	#ifdef __QWM_DGB__
	printk("%s(%d)lpf_mixdiv = %d\n", __func__, __LINE__, mlpf_new);
	#endif

	buf = mlpf_new;
	ds3000_tuner_writereg(state, 0x04, buf);
	buf = (u8)nlpf;
	ds3000_tuner_writereg(state, 0x06, buf);
	ds3000_tuner_writereg(state, 0x51, 0x1b);
	ds3000_tuner_writereg(state, 0x51, 0x1f);
	ds3000_tuner_writereg(state, 0x50, 0x04);
	ds3000_tuner_writereg(state, 0x50, 0x00);
	msleep(5);

	ds3000_tuner_writereg(state, 0x51, 0x1e);
	ds3000_tuner_writereg(state, 0x51, 0x1f);
	ds3000_tuner_writereg(state, 0x50, 0x01);
	ds3000_tuner_writereg(state, 0x50, 0x00);
	msleep(60);

	buf = ds3000_tuner_readreg(state, 0x21);
	buf &= 0x0f;
	if(buf < 3)
	{
		buf = ds3000_tuner_readreg(state, 0x3d);
		buf &= 0x0f;
		if(buf == 15)
		{
			// qwm debug tuner register
			#ifdef __QWM_DGB__
			printk("%s(%d)buf =15 0x60 = 0x61\n", __func__, __LINE__);
			#endif
			ds3000_tuner_writereg(state, 0x60, 0x61);
			ds3000_tuner_writereg(state, 0x51, 0x17);  
			ds3000_tuner_writereg(state, 0x51, 0x1f);   
			ds3000_tuner_writereg(state, 0x50, 0x08);       
			ds3000_tuner_writereg(state, 0x50, 0x00);
		}
	}

	g_tuner_freq_offset_KHz = (s32)((ndiv - ndiv%2 + 1024) * DS3000_XTAL_FREQ / 
				(K + 8)/(div4 + 1) / 2 - state->dcur.frequency);
	// 'mt_fe_tn_set_freq_ts2020' end

	#ifdef __QWM_DGB__
	printk("%s(%d)div4 = %d\n", __func__, __LINE__, div4);
	printk("%s(%d)state->dcur.frequency = %d\n", __func__, __LINE__, state->dcur.frequency);
	printk("%s(%d)g_tuner_freq_offset_KHz = %d\n", __func__, __LINE__, g_tuner_freq_offset_KHz);
	#endif
				
	// qwm debug tuner register
	#ifdef __QWM_DGB__
	buf = ds3000_tuner_readreg(state, 0x07);
	printk("%s(%d)tuner 0x07 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x10);
	printk("%s(%d)tuner 0x10 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x60);
	printk("%s(%d)tuner 0x60 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x08);
	printk("%s(%d)tuner 0x08 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x00);
	printk("%s(%d)tuner 0x00 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x03);
	printk("%s(%d)tuner 0x03 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x04);
	printk("%s(%d)tuner 0x04 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x01);
	printk("%s(%d)tuner 0x01 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x02);
	printk("%s(%d)tuner 0x02 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x26);
	printk("%s(%d)tuner 0x26 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x50);
	printk("%s(%d)tuner 0x50 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x51);
	printk("%s(%d)tuner 0x51 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_tuner_readreg(state, 0x06);
	printk("%s(%d)tuner 0x06 = 0x%02X\n", __func__, __LINE__, buf);
	#endif
	//////////////////////////////////////////////////////////////

	return 0;
}

// qwm add at 2010.4.14
static int ds3000_set_demod(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	u32 i;
	u8 buf, buf2, value, tmp1, tmp2;
	
	g_auto_tune_cnt++;

	// qwm add note: equal '_mt_fe_dmd_ds3k_set_demod'
	buf = ds3000_readreg(state, 0x08);

	switch (c->delivery_system) {
	case SYS_DVBS:
		// qwm add at 2010.4.12
		buf &= ~0x04;
		ds3000_writereg(state, 0x08, buf);

		/* initialise the demod in DVB-S mode */
		// '_mt_fe_dmd_ds3k_init_reg'
		for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
			ds3000_writereg(state,
				ds3000_dvbs_init_tab[i],
				ds3000_dvbs_init_tab[i + 1]);
		// qwm modified at 2010.4.12
		// MtFeTSOut_Max_Clock_16_MHz
		buf = 3;
		buf2 = 3;
		value = ds3000_readreg(state, 0xfe);
		#ifdef __QWM_DGB__
		printk("%s(%d) 0xfe = 0x%02X\n", __func__, __LINE__, value);
		#endif
		value &= 0xc0;
		//value |= 0x1b;
		value |= ((u8)((buf<<3) + buf2));
		// end modified
		ds3000_writereg(state, 0xfe, value);
		break;
	case SYS_DVBS2:
		// qwm add at 2010.4.12
		buf |= 0x04;
		ds3000_writereg(state, 0x08, buf);
		/* initialise the demod in DVB-S2 mode */
		for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
			ds3000_writereg(state,
				ds3000_dvbs2_init_tab[i],
				ds3000_dvbs2_init_tab[i + 1]);
		// MtFeTSOut_Max_Clock_16_MHz
		tmp1 = 5;
		tmp2 = 4;
		value = (u8)((tmp1<<4) + tmp2);
		//ds3000_writereg(state, 0xfe, 0x54);
		ds3000_writereg(state, 0xfe, value);
		break;
	default:
		return 1;
	}

	/* enable 27MHz clock output */
	// qwm add at 2010.4.12
	// !MT_FE_ENABLE_27MHZ_CLOCK_OUT
	buf = ds3000_readreg(state, 0x29);
	#ifdef __QWM_DGB__
	printk("%s(%d)buf = 0x%02X\n", __func__, __LINE__, buf);
	#endif
	buf |= 0x80;
	ds3000_writereg(state, 0x29, buf); //0x80);
	
	// !MT_FE_ENABLE_13_P_5_MHZ_CLOCK_OUT
	buf = ds3000_readreg(state, 0x29);
	#ifdef __QWM_DGB__
	printk("%s(%d)buf = 0x%02X\n", __func__, __LINE__, buf);
	#endif
	buf &= ~0x10;
	ds3000_writereg(state, 0x29, buf); //0x80);
	/* enable ac coupling */
	// MT_FE_ENABLE_AC_COUPLING
	ds3000_writereg(state, 0x25, 0x8a);

	/* enhance symbol rate performance */
	// MT_FE_ENHANCE_PERFORMANCE != 0
	if ((state->dcur.symbol_rate / 1000) <= 5000) {
		value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
		#ifdef __QWM_DGB__
		printk("%s(%d)val_0xc8 = 0x%02X\n", __func__, __LINE__, value);
		#endif
		if (value % 2 != 0)
			value++;
		ds3000_writereg(state, 0xc3, 0x0d);
		ds3000_writereg(state, 0xc8, value);
		ds3000_writereg(state, 0xc4, 0x10);
		ds3000_writereg(state, 0xc7, 0x0e);
	} else if ((state->dcur.symbol_rate / 1000) <= 10000) {
		value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
		#ifdef __QWM_DGB__
		printk("%s(%d)val_0xc8 = 0x%02X\n", __func__, __LINE__, value);
		#endif
		if (value % 2 != 0)
			value++;
		ds3000_writereg(state, 0xc3, 0x07);
		ds3000_writereg(state, 0xc8, value);
		ds3000_writereg(state, 0xc4, 0x09);
		// qwm modified at 2010.4.10
		ds3000_writereg(state, 0xc7, 0x0a); // 0x12);
	} else if ((state->dcur.symbol_rate / 1000) <= 20000) {
		value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
		// qwm modified at 2010.4.10
		#ifdef __QWM_DGB__
		printk("%s(%d)val_0xc3 = 0x%02X\n", __func__, __LINE__, value);
		#endif
		ds3000_writereg(state, 0xc3, 0x10); //value);
		ds3000_writereg(state, 0xc8, 0x3e); //0x0e);
		ds3000_writereg(state, 0xc4, 0x04);	// 0x07
		ds3000_writereg(state, 0xc7, 0x14); //0x18);
	} else {
		value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
		// qwm modified at 2010.4.10
		//value = (u8)((2*129032 + (state->dcur.symbol_rate / 1000)) / 
		//		(2*(state->dcur.symbol_rate / 1000)));
		#ifdef __QWM_DGB__
		printk("%s(%d)val_0xc3 = 0x%02X\n", __func__, __LINE__, value);
		#endif
		ds3000_writereg(state, 0xc3, value);
		ds3000_writereg(state, 0xc8, 0x0a);
		ds3000_writereg(state, 0xc4, 0x05);
		ds3000_writereg(state, 0xc7, 0x12); //0x24);
	}
	
	ds3000_set_symbolrate(state, state->dcur.symbol_rate);

	/* co-channel interference cancellation disabled */
	// qwm add at 2010.4.10. equal '_mt_fe_dmd_ds3k_set_CCI'
	buf = ds3000_readreg(state, 0x56);
	buf &= ~0x01;		// CCI_on
	ds3000_writereg(state, 0x56, buf);
	#ifdef __QWM_DGB__
	printk("%s(%d)0x56 = 0x%02X\n", __func__, __LINE__, buf);
	#endif

	/* equalizer disabled */
	// qwm add at 2010.4.12
	//ds3000_writereg(state, 0x76, 0x00);
	buf = ds3000_readreg(state, 0x76);
	#ifdef __QWM_DGB__
	printk("%s(%d)0x76 = 0x%02X\n", __func__, __LINE__, buf);
	#endif
	buf &= ~0x80;
	ds3000_writereg(state, 0x76, buf);

	ds3000_set_ts_out(fe, 3);		//MtFeTsOutMode_Parallel

	// qwm add for debug at 2010.4.12
	#ifdef __QWM_DGB__
	buf = ds3000_readreg(state, 0x07);
	printk("%s(%d)DS3000 0x07 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x08);
	printk("%s(%d)DS3000 0x08 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xc6);
	printk("%s(%d)DS3000 0xc6 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x25);
	printk("%s(%d)DS3000 0x25 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x29);
	printk("%s(%d)DS3000 0x29 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xfe);
	printk("%s(%d)DS3000 0xfe = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xc3);
	printk("%s(%d)DS3000 0xc3 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xc8);
	printk("%s(%d)DS3000 0xc8 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xc4);
	printk("%s(%d)DS3000 0xc4 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xc7);
	printk("%s(%d)DS3000 0xc7 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x76);
	printk("%s(%d)DS3000 0x76 = 0x%02X\n", __func__, __LINE__, buf);
	/*
	buf = ds3000_readreg(state, 0x61);
	printk("%s(%d)DS3000 0x61 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x62);
	printk("%s(%d)DS3000 0x62 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x56);
	printk("%s(%d)DS3000 0x56 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xb2);
	printk("%s(%d)DS3000 0xb2 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x5f);
	printk("%s(%d)DS3000 0x5f = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x5e);
	printk("%s(%d)DS3000 0x5e = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0x00);
	printk("%s(%d)DS3000 0x00 = 0x%02X\n", __func__, __LINE__, buf);
	buf = ds3000_readreg(state, 0xb2);
	printk("%s(%d)DS3000 0xb2 = 0x%02X\n", __func__, __LINE__, buf);
	*/
	#endif

	return 0;
}

static int ds3000_tune(struct dvb_frontend *fe,
				struct dvb_frontend_parameters *p)
{
	struct ds3000_state *state = fe->demodulator_priv;
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	int ret = 0, retune, i;

	u8 status; //, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
	u16 value; //ndiv;
	//u32 f3db;
	// qwm add at 2010.4.10
	//u32 N;
	//u8 div4, K, buf, buf2, changePLL;	// qwm add at 2010.4.10
	s16	lpf_offset_KHz;
	u32	freq_tmp_KHz;
	s32 tmp;

	// qwm add at 2010.4.14
	g_auto_tune_cnt = 0;
	g_cci_detect	= 1;

	dprintk("%s() ", __func__);

	/* Load the firmware if required */
	ret = ds3000_firmware_ondemand(fe);
	if (ret != 0) {
		printk(KERN_ERR "%s: Unable initialise the firmware\n",
								__func__);
		return ret;
	}
	// qwm add at 2010.4.21
	g_load_firmware = 1;

	state->dnxt.delivery = c->modulation;
	state->dnxt.frequency = c->frequency;
	state->dnxt.rolloff = 2; /* fixme */
	state->dnxt.fec = c->fec_inner;

	ret = ds3000_set_inversion(state, p->inversion);
	if (ret !=  0)
		return ret;

	ret = ds3000_set_symbolrate(state, c->symbol_rate);
	if (ret !=  0)
		return ret;

	/* discard the 'current' tuning parameters and prepare to tune */
	ds3000_clone_params(fe);

	retune = 1;	/* try 1 times */
	#if 0
	dprintk("%s:   retune = %d\n", __func__, retune);
	dprintk("%s:   frequency   = %d\n", __func__, state->dcur.frequency);
	dprintk("%s:   symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
	dprintk("%s:   FEC	 = %d \n", __func__,
		state->dcur.fec);
	dprintk("%s:   Inversion   = %d\n", __func__, state->dcur.inversion);
	#else
	printk("%s:   retune = %d\n", __func__, retune);
	printk("%s:   frequency   = %d\n", __func__, state->dcur.frequency);
	printk("%s:   symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
	printk("%s:   FEC	 = %d \n", __func__, state->dcur.fec);
	printk("%s:   Inversion   = %d\n", __func__, state->dcur.inversion);
	#endif
	
	// qwm add at 2010.4.19
	freq_tmp_KHz  	=  state->dcur.frequency;
	lpf_offset_KHz 	= 0;
	if (state->dcur.symbol_rate/1000 < 5000)
	{
		lpf_offset_KHz = 3000; //FREQ_OFFSET_AT_SMALL_SYM_RATE_KHz;
		freq_tmp_KHz  += 3000; //FREQ_OFFSET_AT_SMALL_SYM_RATE_KHz;
	}

	do {
		/* Reset status register */
		status = 0;
		/* Tune */
		// qwm modified		/* normalized symbol rate rounded to the closest integer */
		// qwm modified at 2010.4.10. equal '_mt_fe_dmd_ds3k_set_sym_rate'
		//value = (((state->dcur.symbol_rate / 1000) << 16) +
		//		(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
		value = (((state->dcur.symbol_rate / 1000) << 15) +
				(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
		#ifdef __QWM_DGB__
		printk("%s(%d)value = 0x%02X\n", __func__, __LINE__, value);
		#endif
		//ds3000_writereg(state, 0x61, value & 0x00ff);
		//ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);

		// set tuner
		ds3000_set_tuner(fe, state->dcur.frequency, state->dcur.symbol_rate, 0);

		/* unknown */
		/* unknown */

		/*
		ds3000_tuner_writereg(state, 0x60, value);
		ds3000_tuner_writereg(state, 0x51, 0x17);
		ds3000_tuner_writereg(state, 0x51, 0x1f);
		ds3000_tuner_writereg(state, 0x50, 0x08);
		ds3000_tuner_writereg(state, 0x50, 0x00);
		*/

		/* unknown */
	

		/* ds3000 global reset */
		ds3000_writereg(state, 0x07, 0x80);
		ds3000_writereg(state, 0x07, 0x00);
		/* ds3000 build-in uC reset */
		ds3000_writereg(state, 0xb2, 0x01);
		/* ds3000 software reset */
		ds3000_writereg(state, 0x00, 0x01);
		
		// '_mt_fe_dmd_ds3k_set_demod'
		ds3000_set_demod(fe);

		/* normalized symbol rate rounded to the closest integer */
		// qwm modified at 2010.4.10. equal '_mt_fe_dmd_ds3k_set_sym_rate'
		//value = (((state->dcur.symbol_rate / 1000) << 16) +
		//		(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
		/*
		value = (((state->dcur.symbol_rate / 1000) << 15) +
				(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
		#ifdef __QWM_DGB__
		printk("%s(%d)value = 0x%02X\n", __func__, __LINE__, value);
		#endif
		ds3000_writereg(state, 0x61, value & 0x00ff);
		ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
		*/



		/*ds3000_writereg(state, 0x08, 0x03);
		ds3000_writereg(state, 0xfd, 0x22);
		ds3000_writereg(state, 0x08, 0x07);
		ds3000_writereg(state, 0xfd, 0x42);
		ds3000_writereg(state, 0x08, 0x07);*/

		/* TODO: calculate and set carrier offset */
		// qwm add at 2010.4.12. 
		//calculate & set carrier offset
		tmp = g_tuner_freq_offset_KHz + (freq_tmp_KHz - state->dcur.frequency);
		printk("%s(%d)tuner set_carrier_offset tmp = %d\n", __func__, __LINE__, tmp);
		tmp *= 65536;
		tmp = (s32)((2*g_tuner_freq_offset_KHz + 96000)/(2*96000));
		if(tmp < 0)
			tmp += 65536;
		ds3000_writereg(state, 0x5f, (u8)(tmp>>8));
		ds3000_writereg(state, 0x5e, (u8)(tmp&0xFF));

		/* ds3000 out of software reset */
		ds3000_writereg(state, 0x00, 0x00);
		/* start ds3000 build-in uC */
		ds3000_writereg(state, 0xb2, 0x00);
		// end 'mt_fe_dmd_ds3k_connect'

		/* wait before retrying */
		for (i = 0; i < 30 ; i++) {
			if (ds3000_is_tuned(fe)) {
				dprintk("%s: Tuned\n", __func__);
				ds3000_dump_registers(fe);
				goto tuned;
			}
			msleep(1);
		}

		dprintk("%s: Not tuned\n", __func__);
		ds3000_dump_registers(fe);

	} while (--retune);
	

tuned:
	return ret;
}

static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
{
	dprintk("%s()\n", __func__);
	return DVBFE_ALGO_SW;
}

/*
 * Initialise or wake up device
 *
 * Power config will reset and load initial firmware if required
 */
static int ds3000_initfe(struct dvb_frontend *fe)
{
	struct ds3000_state *state = fe->demodulator_priv;

#ifdef __QWM_DGB__
	printk("%s(%d)***********************\n", __func__, __LINE__);
#endif
	dprintk("%s()\n", __func__);

	// qwm add at 2010.4.17
	//ds3000_firmware_ondemand(fe);
	//ds3000_set_LNB(state, 1, 0, fe->dtv_property_cache.voltage);

	return 0;
}

/* Put device to sleep */
static int ds3000_sleep(struct dvb_frontend *fe)
{
	dprintk("%s()\n", __func__);
	
	return 0;
}

static struct dvb_frontend_ops ds3000_ops = {

	.info = {
		.name = "Montage Technology DS3000/TS2020",
		.type = FE_QPSK,
		.frequency_min = 950000,
		.frequency_max = 2150000,
		.frequency_stepsize = 1011, /* kHz for QPSK frontends */
		.frequency_tolerance = 5000,
		.symbol_rate_min = 1000000,
		.symbol_rate_max = 45000000,
		.caps = FE_CAN_INVERSION_AUTO |
			FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
			FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
			FE_CAN_2G_MODULATION |
			FE_CAN_QPSK | FE_CAN_RECOVER
	},

	.release = ds3000_release,

	.init = ds3000_initfe,
	//.release = ds3000_release,
	.sleep = ds3000_sleep,
	.read_status = ds3000_read_status,
	.read_ber = ds3000_read_ber,
	.read_signal_strength = ds3000_read_signal_strength,
	.read_snr = ds3000_read_snr,
	.read_ucblocks = ds3000_read_ucblocks,
	.set_tone = ds3000_set_tone,
	.diseqc_send_master_cmd = ds3000_send_diseqc_msg,
	.diseqc_send_burst = ds3000_diseqc_send_burst,
	.get_frontend_algo = ds3000_get_algo,

	.set_property = ds3000_set_property,
	.get_property = ds3000_get_property,
	.set_frontend = ds3000_tune,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");

MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
			"DS3000/TS2020 hardware");
MODULE_AUTHOR("Konstantin Dimitrov");
MODULE_LICENSE("GPL");
